1. Field of the Invention
The present invention relates to a semiconductor device, and more particularity relates to a semiconductor device using an IGBT (Insulated Gate Bipolar Transistor) as a selective element.
2. Description of Related Art
In recent years, a semiconductor device including a semiconductor memory device such as a DRAM (Dynamic Random Access Memory) and a PC-RAM (Phase Change Random Access Memory) has an increasingly smaller area that can be allocated to a selective element (such as a cell transistor of a DRAM) along with the progress of downscaling. As the allocated area becomes smaller, the value of a current flowing to a selective element (such as a drain current of a field-effect transistor and a write current Icell in a DRAM) becomes small. Therefore, to secure a certain level of the current value, constituting a selective element by a combination of a MOS (Metal Oxide Semiconductor) transistor and a bipolar transistor has been examined.
U.S. Pat. No. 6,576,921 discloses an example of a cell transistor of a phase-change memory that uses such a selective element. In this conventional example, word lines are formed on a surface of a P-type substrate via a gate insulating film, and first and second N-type diffusion regions are formed in a region within a substrate surface close to both sides of the word lines. In the second N-type diffusion region, a P-type diffusion region is further provided in a region within a substrate surface far from a gate electrode. With this arrangement, a MOS transistor is formed by the P-type substrate, the first and second N-type diffusion regions, the gate insulating film, and the gate electrode, and a bipolar transistor is formed by the P-type substrate, the second N-type diffusion region, and the P-type diffusion region. The second N-type diffusion region functions as both a drain of the MOS transistor and a base of the bipolar transistor.
The P-type substrate and the first N-type diffusion region are grounded. Meanwhile, the P-type diffusion region is connected to bit lines via a phase-change memory element. When a voltage that exceeds a threshold value of the MOS transistor is applied to word lines in this state, the MOS transistor is turned on, and a drain current flows. This drain current flows to the second N-type diffusion region, and turns on the bipolar transistor. Because the phase-change memory element is connected to the ground, writing and reading can be performed to the phase-change memory element by controlling a voltage applied to the bit lines.
However, the selective element described in U.S. Pat. No. 6,576,921 has a problem that the length in a lateral direction becomes large. That is, according to the configuration of the selective element described above, the first N-type diffusion region, the word lines, the second N-type diffusion region, and the P-type diffusion region are arranged in a bit line direction. Therefore, even when these regions and the word lines are formed in a minimum feature size F, respectively, the length of 4F in the bit line direction becomes necessary. Consequently, a configuration capable of reducing the length of a selective element in a bit line direction has been demanded.